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S3C9442/C9444/F9444/C9452/C9454/F9454
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations.
S3C9442/C9444/C9452/C9454 MICROCONTROLLER
The S3C9442/C9444/C9452/C9454 single-chip 8-bit microcontroller is designed for useful A/D converter , SIO application field. The S3C9442/C9444/C9452/C9454 uses powerful SAM88RCRI CPU and S3C9442/C9444/C9452/C9454 architecture. The internal register file is logically expanded to increase the onchip register space. The S3C9442/C9444/C9452/C9454 has 2K/4K bytes of on-chip program ROM and 208 bytes of RAM. The S3C9442/C9444/C9452/C9454 is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring simple timer/counter, PWM. In addition, the S3C9442/C9444/C9452/C9454's advanced CMOS technology provides for low power consumption and wide operating voltage range. Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core: -- Three configurable I/O ports (18 pins) -- Four interrupt sources with one vector and one interrupt level -- One 8-bit timer/counter with time interval mode -- Analog to digital converter with nine input channels and 10-bit resolution -- One 8-bit PWM output The S3C9442/C9444/C9452/C9454 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, PWM, ADC. S3C9452/C9454 is available in a 20/16-pin DIP and a 20-pin SOP package. S3C9452/C9454 is available in a 8-pin and a 8-pin SOP package.
MTP
The S3F9444/F9454 is an MTP (Multi Time Programmable) version of the S3C9442/C9444/C9452/C9454 microcontroller. The S3F9444/F9454 has on-chip 4-Kbyte multi-time programmable flash ROM instead of masked ROM. The S3F9444/F9454 is fully compatible with the S3C9442/C9444/C9452/C9454, in function, in D.C. electrical characteristics and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C9442/C9444/F9444/C9452/C9454/F9454
FEATURES
CPU * * SAM88RCRI CPU core The SAM88RCRI core is low-end version of the current SAM87 core. Timer/Counters * * One 8-bit basic timer for watchdog function One 8-bit timer/counter with time interval modes
A/D Converter Memory * * 2/4-Kbyte internal program memory 208-byte general purpose register area Oscillation Frequency Instruction Set * * 41 instructions The SAM88RCRI core provides all the SAM87 core instruction except the word-oriented instruction, multiplication, division, and some one-byte instruction. * * * 1 MHz to 10 MHz external crystal oscillator Maximum 10 MHz CPU clock Internal RC: 3.2 MHz (typ.), 0.5 MHz (typ.) in VDD = 5 V * * Nine analog input pins 10-bit conversion resolution
Operating Temperature Range Instruction Execution Time * 400 ns at 10 MHz fOSC (minimum) Operating Voltage Range Interrupts * * 4 interrupt sources with one vector One interrupt level Smart Option Package Types * S3C9452/C9454: - 20-DIP-300A - 20-SOP-375 - 16-DIP-300A S3C9442/C9444 - 8-DIP-300 - 8-SOP-225 * 2.0 V (LVR Level) to 5.5 V * - 40C to + 85C
General I/O * * Three I/O ports (Max 18 pins) Bit programmable ports
8-bit High-speed PWM * * 8-bit PWM 1-ch (Max: 156 kHz) 6-bit base + 2-bit extension
*
Built-in reset Circuit * Low voltage detector for safe reset
1-2
S3C9442/C9444/F9444/C9452/C9454/F9454
PRODUCT OVERVIEW
BLOCK DIAGRAM
XIN XOUT
OSC Port 0 Port I/O and Interrupt Control Basic Timer
P0.0/ADC0/INT0 P0.1/ADC1/INT1 P0.2/ADC2 P0.7/ADC7
P1.0 Timer 0 88RCRI SAMRI CPU ADC P2.0/T0 PWM 2 KB ROM 4 KB ROM 208 Byte Register file Port 2 P2.1 Port 1 P1.1 P1.2
...
ADC0-ADC8
...
P0.6/PWM
P2.6
NOTE:
P1.2 is used as input only
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C9442/C9444/F9444/C9452/C9454/F9454
PIN ASSIGNMENTS
VSS XIN/P1.0 XOUT/P1.1
RESET/P1.2
1 2 3 4 5 6 7 8 9 10
20 19 18 17
VDD P0.0/ADC0/INT0 P0.1/ADC1/INT1 P0.2/ADC2 P0.3/ADC3 P0.4/ADC4 P0.5/ADC5 P0.6/ADC6/PWM P0.7/ADC7 P2.6/ADC8/CLO
P2.0/T0 P2.1 P2.2 P2.3 P2.4 P2.5
S3C9452/C9454
(20-DIP-300A/ 20-SOP-375)
16 15 14 13 12 11
Figure 1-2. Pin Assignment Diagram (20-Pin DIP/SOP Package)
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S3C9442/C9444/F9444/C9452/C9454/F9454
PRODUCT OVERVIEW
VSS XIN/P1.0 XOUT/P1.1
RESET /P1.2
1 2 3 4 5 6 7 8
16 15 14
VDD P0.0/ADC0/INT0 P0.1/ADC1/INT1 P0.2/ADC2 P0.3/ADC3 P0.4/ADC4 P0.5/ADC5 P0.6/ADC6/PWM
S3C9452/C9454
(16-DIP-300A)
13 12 11 10 9
P2.0/T0 P2.1 P2.2 P2.3
Figure 1-3. Pin Assignment Diagram (16-Pin DIP Package)
VSS XIN/P1.0 XOUT/P1.1
RESET/P1.2
1 2 3 4
S3C9442/C9444
(8-DIP-300 8-SOP-225)
8 7 6 5
VDD P0.0/ADC0/INT0 P0.1/ADC1/INT1 P0.2/ADC2
Figure 1-4. Pin Assignment Diagram (8-Pin DIP/SOP Package)
1-5
PRODUCT OVERVIEW
S3C9442/C9444/F9444/C9452/C9454/F9454
PIN DESCRIPTIONS
Table 1-1. S3C9452/C9454 Pin Descriptions Pin Name P0.0-P0.7 In/Out I/O Pin Description Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port0 pins can also be used as A/D converter input, PWM output or external interrupt input. Bit-programmable I/O port for Schmitt trigger input or push-pull, open-drain output. Pull-up resistors or pull-down resistors are assignable by software. Schmitt trigger input port Bit-programmable I/O port for Schmitt trigger input or push-pull, open-drain output. Pull-up resistors are assignable by software. Crystal/Ceramic, or RC oscillator signal for system clock. Internal LVR or External RESET Voltage input pin and ground System clock output port External interrupt input port 8-Bit high speed PWM output Timer0 match output A/D converter input E-1 E-1 E-1 E-1 E-1 E B Pin Type E-1 Share Pins ADC0-ADC7 INT0/INT1 PWM XIN, XOUT
P1.0-P1.1
I/O
E-2
P1.2 P2.0-P2.6
I I/O
B E E-1
RESET
- ADC8/CLO T0 P1.0-P1.1 P1.2 - P2.6 P0.0, P0.1 P0.6 P2.0 P0.0-P0.7 P2.6
XIN, XOUT
RESET
- I - O I O O I
VDD, VSS CLO INT0-INT1 PWM T0 ADC0-ADC8
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S3C9442/C9444/F9444/C9452/C9454/F9454
PRODUCT OVERVIEW
PIN CIRCUITS
VDD
P-channel IN N-channel IN
Figure 1-5. Pin Circuit Type A
Figure 1-6. Pin Circuit Type B
VDD VDD Pull-up Enable Out Output DIsable Data Output Disable
Data
Circuit Type C
I/O
Digital Input
Figure 1-7. Pin Circuit Type C
Figure 1-8. Pin Circuit Type D
1-7
PRODUCT OVERVIEW
S3C9442/C9444/F9444/C9452/C9454/F9454
VDD Open-drain Enable P2CONH P2CONL Alternative Output P2.x VDD Pull-up enable
P-CH M U X Data I/O N-CH
Output Disable (Input Mode) Digital Input
Analog Input Enable ADC
Figure 1-9. Pin Circuit Type E
VDD
P0CONH Alternative Output P0.x
VDD
Pull-up enable
P-CH M U X Data I/O N-CH
Output Disable (Input Mode) Digital Input
Interrupt Input Analog Input Enable ADC
Figure 1-10. Pin Circuit Type E-1
1-8
S3C9442/C9444/F9444/C9452/C9454/F9454
PRODUCT OVERVIEW
VDD Open-drain Enable VDD Pull-up enable
P1.x I/O Output Disable (Input Mode) Pull-down enable
Digital Input XIN XOUT
Figure 1-11. Pin Circuit Type E-2
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S3C9442/C9444/F9444/C9452/C9454/F9454
ELECTRICAL DATA
13
OVERVIEW
ELECTRICAL DATA
In this section, the following S3C9442/C9444/C9452/C9454 electrical characteristics are presented in tables and graphs: -- Absolute maximum ratings -- D.C. electrical characteristics -- A.C. electrical characteristics -- Input Timing Measurement Points -- Oscillator characteristics -- Oscillation stabilization time -- Operating Voltage Range -- Schmitt trigger input characteristics -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by a RESET -- A/D converter electrical characteristics -- LVR circuit characteristics -- LVR reset Timing
13-1
ELECTRICAL DATA
S3C9442/C9444/F9444/C9452/C9454/F9454
Table 13-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current high Symbol VDD VI VO IOH IOL TA TSTG All ports All output ports One I/O pin active All I/O pins active Output current low One I/O pin active All I/O pins active Operating temperature Storage temperature - - Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 25 - 80 + 30 + 150 - 40 to + 85 - 65 to + 150 C C mA Unit V V V mA
13-2
S3C9442/C9444/F9444/C9452/C9454/F9454
ELECTRICAL DATA
Table 13-2. DC Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Input high voltage Input low voltage Output high voltage Output low voltage Input high leakage current Input low leakage current Output high leakage current Output low leakage current Pull-up resistors Pull-down resistors Supply current Symbol VIH1 VIH2 VIL1 VIL2 VOH VOL ILIH1 ILIH2 ILIL1 ILIL2 ILOH ILOL RP RP IDD1
RESET
Conditions Ports 0, 1, 2 and XIN and XOUT Ports 0, 1, 2 and
RESET
Min 0.8 VDD VDD- 0.1
Typ -
Max VDD
Unit V
VDD= 2.0 to 5.5 V
VDD= 2.0 to 5.5 V
-
-
0.2 VDD 0.1
V
XIN and XOUT IOH = - 10 mA ports 0, 1, 2 IOL = 25 mA port 0, 1, and 2 All input except ILIH2 XIN, XOUT All input except ILIL2 and RESET XIN, XOUT All output pins All output pins VIN = 0 V Ports 0, 1, 2 VIN = 0 V Ports 1 Run mode 10 MHz CPU clock 3 MHz CPU clock Idle mode 10 MHz CPU clock 3 MHz CPU clock Stop mode VDD= 4.5 to 5.5 V VDD= 4.5 to 5.5 V VIN = VDD VIN = VDD VIN = 0 V VIN = 0 V VOUT = VDD VOUT = 0 V VDD = 5 V VDD = 5 V VDD = 4.5 to 5.5 V VDD = 2.0 V VDD = 4.5 to 5.5 V VDD = 2.0 V VDD = 4.5 to 5.5 V (LVR disable) VDD = 4.5 to 5.5 V (LVR enable) VDD = 2.6 V (LVR enable) - - - - 25 25
-
VDD-1.5 - -
VDD- 0.4 0.4 -
- 2.0 1 20
V V uA
-
-
-1 -20
uA
- - 50 50 5 2 2 0.5 0.1 100 30
2 -2 100 100 10 5 4 1.5 5 200 60
uA uA k
mA
IDD2
IDD3
uA
NOTE: In STOP (IDD3), IDLE (IDD2) current, current by ADC module is not included.
13-3
ELECTRICAL DATA
S3C9442/C9444/F9444/C9452/C9454/F9454
Table 13-3. AC Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Interrupt input low width
RESET input
Symbol tINTL tRSL
Conditions INT0, INT1 VDD = 5 V 10 % Input VDD = 5 V 10 %
Min - -
Typ 200 1
Max - -
Unit ns us
low width
tINTL
tINTH
XIN
0.8 VDD 0.2 VDD
Figure 13-1. Input Timing Measurement Points
13-4
S3C9442/C9444/F9444/C9452/C9454/F9454
ELECTRICAL DATA
Table 13-4. Oscillator Characteristics (TA = - 40C to + 85C) Oscillator Main crystal or ceramic Clock Circuit
C1 XIN
Test Condition VDD = 4.5 to 5.5 V
Min 1
Typ -
Max 10
Unit MHz
C2
XOUT
VDD = 2.7 to 4.5 V VDD = 2.0 to 2.7 V External clock (Main System)
XIN
1 1 1
- - -
6 3 10
MHz MHz MHz
VDD = 4.5 to 5.5 V
XOUT
VDD = 2.7 to 4.5 V VDD = 2.0 to 2.7 V External RC oscillator Internal RC Oscillator - VDD = 4.75 to 5.25 V Tolerance:10 % VDD = 4.75 to 5.25 V
1 1 -
- - 4 3.2 0.5
6 3 -
MHz MHz MHz
Table 13-5. Oscillation Stabilization Time (TA = - 40 C to + 85 C, VDD = 3.0 V to 5.5 V) Oscillator Main crystal Main ceramic External clock (main system) Oscillator stabilization wait time Test Condition f OSC > 1.0 MHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input high and low width (tXH, tXL) tWAIT when released by a reset (1) tWAIT when released by an interrupt (2) Min - - 25 - - Typ - - - 216/fOSC - Max 20 10 500 - - Unit ms ms ns ms ms
NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the settings in the basic timer control register, BTCON.
13-5
ELECTRICAL DATA
S3C9442/C9444/F9444/C9452/C9454/F9454
CPU Clock 10 MHz 6 MHz 4 MHz 3 MHz 2 MHz 1 MHz 1 2 2.7 3 4 4.5 5 5.5 6 7
Supply Voltage (V)
Figure 13-2. Operating Voltage Range
VOUT VDD A = 0.2 VDD B = 0.4 VDD C = 0.6 VDD D = 0.8 VDD VSS A B C D
VIN
0.3 VDD
0.7 VDD
Figure 13-3. Schmitt Trigger Input Characteristics Diagram
13-6
S3C9442/C9444/F9444/C9452/C9454/F9454
ELECTRICAL DATA
Table 13-6. Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode Stop mode; VDDDR = 2.0 V Min 2.0 - Typ - 0.1 Max 5.5 5 Unit V uA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Stop Mode Data Retention Mode
RESET Occurs
Oscillation Stabilization Time
~ ~
VDD
RESET
Execution Of Stop Instrction
NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC
Figure 13-4. Stop Mode Release Timing When Initiated by a RESET
~ ~ VDDDR Normal Operating Mode tWAIT 13-7
ELECTRICAL DATA
S3C9442/C9444/F9444/C9452/C9454/F9454
Table 13-7. A/D Converter Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Total accuracy Symbol - Test Conditions VDD = 5.12 V CPU clock = 10 MHz VSS = 0 V f OSC = 10 MHz - - VDD = 5 V VDD = 5 V VDD = 3 V VDD = 5 V power down mode - Min - Typ - Max 3 Unit LSB
Integral linearity error Differential linearity error Offset error of top Offset error of bottom Conversion time (1) Analog input voltage Analog input impedance Analog input current Analog block current (2)
ILE DLE EOT EOB tCON VIAN RAN IADIN IADC
- - - - - VSS 2 - -
- - 1 1 20 - - - 1 0.5 100
2 1 3 2 - VDD - 10 3 1.5 500 nA s V M A mA
NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion.
13-8
S3C9442/C9444/F9444/C9452/C9454/F9454
ELECTRICAL DATA
Table 13-8. LVR Circuit Characteristics (TA = 25 C, VDD = 2.0 V to 5.5 V) Parameter Low voltage reset Symbol VLVR Conditions - Min - Typ 2.3 3.0 3.9 0.3 -
(note)
Max
Unit V
LVR hysteresis voltage Power supply voltage rise time Power supply voltage off time
VHYS tR tOFF
- 10 0.5
V us s
NOTE: 216/fx ( = 6.55 ms at fx = 10 MHz)
tOFF VDD VHYS
tR VLVR,MAX VLVR VHYS VLVR,MIN
Figure 13-5. LVR Reset Timing
13-9
S3C9442/C9444/F9444/C9452/C9454/F9454
MECHANICAL DATA
14
OVERVIEW
MECHANICAL DATA
The S3C9452/C9454 is available in a 20-pin DIP package (Samsung: 20-DIP-300A), a 20-pin SOP package (Samsung: 20-SOP-375), a 16-pin DIP package (Samsung: 16-DIP-300A). Package dimensions are shown in Figure 15-1, 15-2, and 15-3. The S3C9442/C9444 is available in a 8-pin DIP package (SAMSUNG 8-DIP-300A), a 8-pin SOP package (SAMSUNG 8-SOP-225). Package dimensions are shown in figure 14-4 and 14-5.
#20
#11
0-15
6.40 0.20
#1
#10
26.80 MAX 26.40 0.20
0.46 0.10 (1.77) 1.52 0.10 2.54
NOTE:
Dimensions are in millimeters.
Figure 14-1. 20-DIP-300A Package Dimensions
3.30 0.30
0.51 MIN
5.08 MAX
3.25 0.20
0.2
5
+0 - 0 .10 .05
20-DIP-300A
7.62
14-1
MECHANICAL DATA
S3C9442/C9444/F9444/C9452/C9454/F9454
0-8 #20 #11
10.30 0.30
7.50 0.20
20-SOP-375
#1
#10
0.203
13.14 MAX 12.74 0.20
2.50 MAX
2.30 0.10
0.10 MAX
(0.66) 0.40
+ 0.10 - 0.05
1.27
NOTE:
Dimensions are in millimeters.
Figure 14-2. 20-SOP-375 Package Dimensions
14-2
0.05 MIN
0.85 0.20
+ 0.10 - 0.05
9.53
S3C9442/C9444/F9444/C9452/C9454/F9454
MECHANICAL DATA
#16
#9
0-15
6.40 0.20
#1
#8
3.25 0.20
19.80 MAX 19.40 0.20
0.46 0.10 (0.81) 1.50 0.10 2.54
NOTE:
Dimensions are in millimeters.
Figure 14-3. 16-DIP-300A Package Dimensions
3.30 0.30
0.38 MIN
5.08 MAX
0.2
5
+0 - 0 .10 .05
16-DIP-300A
7.62
14-3
MECHANICAL DATA
S3C9442/C9444/F9444/C9452/C9454/F9454
#8
#5
0-15
6.40 0.20
#1
#4
3.40 0.20
9.60 MAX 9.20 0.20
(0.79)
0.46 0.10 1.52 0.10
NOTE:
Dimensions are in millimeters.
Figure 14-4. 8-DIP-300 Package Dimensions
14-4
3.30 0.30
0.33 MIN
2.54
5.08 MAX
0.2
5
+0 - 0 .10 .05
8-DIP-300
7.62
S3C9442/C9444/F9444/C9452/C9454/F9454
MECHANICAL DATA
0-8 #8 #5
3.95 0.20
6.00 0.30
8-SOP-225
0.15
1.55 0.20
5.13 MAX 4.92 0.20
1.80 MAX
0.10 MAX
(0.56)
1.27 0.41 0.10
NOTE:
Dimensions are in millimeters.
Figure 14-5. 8-SOP-225 Package Dimensions
0.1-0.25 MIN
0.50 0.20
#1
#4
+ 0.10 - 0.05
5.72
14-5
S3C9442/C9444/F9444/C9452/C9454/F9454
S3F9444/F9454 MTP
15
OVERVIEW
S3F9444/F9454 MTP
The S3F9444/F9454 single-chip CMOS microcontroller is the MTP (Multi Time Programmable) version of the S3C9442/C9444/C9452/C9454 microcontroller. It has an on-chip Flash ROM instead of masked ROM. The Flash ROM is accessed by serial data format. The S3F9444/F9454 is fully compatible with the S3C9442/C9444/C9452/C9454, in function, in D.C. electrical characteristics, and in pin configuration. Because of its simple programming requirements, the S3F9444/F9454 is ideal for use as an evaluation chip for the S3C9442/C9444/C9452/C9454.
VSS/VSS XIN/P1.0 XOUT/P1.1 VPP/RESET/P1.2 T0/P2.0 P2.1 P2.2 P2.3 P2.4 P2.5
1 2 3 4 5 6 7 8 9 10
20 19 18 17
VDD/VDD P0.0/ADC0/INT0/SCL P0.1/ADC1/INT1/SDA P0.2/ADC2 P0.3/ADC3 P0.4/ADC4 P0.5/ADC5 P0.6/ADC6/PWM P0.7/ADC7 P2.6/ADC8/CLO
S3F9454
16 15 14 13 12 11
NOTE:
The bolds indicate MTP pin name.
Figure 15-1. Pin Assignment Diagram (20-Pin Package)
15-1
S3F9444/F9454 MTP
S3C9442/C9444/F9444/C9452/C9454/F9454
VSS/VSS XIN/P1.0 XOUT/P1.1 VPP/RESET/P1.2 T0/P2.0 P2.1 P2.2 P2.3
1 2 3 4 5 6 7 8
16 15 14 13
VDD/VDD P0.0/ADC0/INT0/SCL P0.1/ADC1/INT1/SDA P0.2/ADC2 P0.3/ADC3 P0.4/ADC4 P0.5/ADC5 P0.6/ADC6/PWM
S3F9454
12 11 10 9
NOTE:
The bolds indicate MTP pin name.
Figure 15-2. Pin Assignment Diagram (16-Pin Package)
VSS/VSS XIN/P1.0 XOUT/P1.1 VPP/RESET/P1.2
1 2 3 4
8
VDD/VDD P0.0/ADC0/INT0/SCL P0.1/ADC1/INT1/SDA P0.2/ADC2
S3F9444
7 6 5
NOTE:
The bolds indicate MTP pin name.
Figure 15-3. Pin Assignment Diagram (8-Pin Package)
15-2
S3C9442/C9444/F9444/C9452/C9454/F9454
S3F9444/F9454 MTP
Table 15-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip Pin Name P0.1 Pin Name SDA Pin No. 18 (20-pin) 14 (16-pin) 19 (20-pin) 15 (16-pin) 4 During Programming I/O I/O Function Serial data pin (output when reading, Input when writing) Input and push-pull output port can be assigned Serial clock pin (input only pin) Power supply pin for flash ROM cell writing (indicates that MTP enters into the writing mode). When 12.5 V is applied, MTP is in writing mode and when 5 V is applied, MTP is in reading mode. (Option) Logic power supply pin.
P0.0
RESET, P1.2
SCL VPP
I I
VDD/VSS
VDD/VSS
20 (20-pin), 16 (16-pin) 1 (20-pin), 1 (16-pin)
I
Table 15-2. Comparison of S3F9444/F9454 and S3C9442/C9444/C9452/C9454 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3F9444/F9454 4 Kbyte Flash ROM 2.0 V to 5.5 V VDD = 5 V, VPP = 12.5 V 20 DIP/20 SOP/16 DIP/8 DIP/8 SOP User Program multi time Programmed at the factory S3C9442/C9444/C9452/C9454 2K/4K byte mask ROM 2.0 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP pin of the S3F9444/F9454 Flash ROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-3. Operating Mode Selection Criteria VDD 5V VPP 5V 12.5 V 12.5 V 12.5 V REG/MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 Mode Flash ROM read Flash ROM program Flash ROM verify Flash ROM read protection
NOTE: "0" means Low level; "1" means High level.
15-3

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